a AD548 precision, low power bifet op amp rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. features enhanced replacement for lf441 and tl061 dc performance: 200 m a max quiescent current 10 pa max bias current, warmed up (AD548c) 250 m v max offset voltage (AD548c) 2 m v/ 8 c max drift (AD548c) 2 m v p-p noise, 0.1 hz to 10 hz ac performance: 1.8 v/ m s slew rate 1 mhz unity gain bandwidth available in plastic, hermetic cerdip and hermetic metal can packages and in chip form available in tape and reel in accordance with eia-481a standard mil-std-883b parts available dual version available: ad648 surface mount (soic) package available product description the AD548 is a low power, precision monolithic operational amplifier. it offers both low bias current (10 pa max, warmed up) and low quiescent current (200 m a max) and is fabricated with ion-implanted fet and laser wafer trimming technologies. input bias current is guaranteed over the AD548s entire common-mode voltage range. the economical j grade has a maximum guaranteed input offset voltage of less than 2 mv and an input offset voltage drift of less than 20 m v/ c. the c grade reduces input offset voltage to less than 0.25 mv and offset voltage drift to less than 2 m v/ c. this level of dc precision is achieved utilizing analogs laser wafer drift trimming process. the combination of low quiescent cur- rent and low offset voltage drift minimizes changes in input off- set voltage due to self-heating effects. four additional grades are offered over the commercial, industrial and military temperature ranges. the AD548 is recommended for any dual supply op amp appli- cation requiring low power and excellent dc and ac perfor- mance. in applications such as battery-powered, precision instrument front ends and cmos dac buffers, the AD548s excellent combination of low input offset voltage and drift, low bias current and low 1/f noise reduces output errors. high com- mon-mode rejection (86 db, min on the c grade) and high open-loop gain ensures better than 12-bit linearity in high im- pedance, buffer applications. the AD548 is pinned out in a standard op amp configuration and is available in six performance grades. the AD548j and AD548k are rated over the commercial temperature range of 0 c to +70 c. the AD548a, AD548b and AD548c are rated over the industrial temperature range of C40 c to +85 c. the AD548s is rated over the military temperature range of C55 c to +125 c and is available processed to mil-std-883b, rev. c. the AD548 is available in an 8-pin plastic mini-dip, cerdip, to-99 metal can, surface mount (soic), or in chip form. product highlights 1. a combination of low supply current, excellent dc and ac performance and low drift makes the AD548 the ideal op amp for high performance, low power applications. 2. the AD548 is pin compatible with industry standard op amps such as the lf441, tl061, and ad542, enabling de- signers to improve performance while achieving a reduction in power dissipation of up to 85%. 3. guaranteed low input offset voltage (2 mv max) and drift (20 m v/ c max) for the AD548j are achieved utilizing analog devices laser drift trimming technology, eliminating the need for external trimming. 4. analog devices specifies each device in the warmed-up con- dition, insuring that the device will meet its published specifi- cations in actual use. 5. a dual version, the ad648 is also available. 6. enhanced replacement for lf441 and tl061. connection diagrams plastic mini-dip (n) package, cerdip (q) package and soic (r)package AD548 offset null output nc v offset null noninverting input 6 7 1 3 4 5 2 8 v+ note : pin 4 connected to case nc = no connect inverting input 1 2 3 4 8 7 6 5 AD548 offset null v+ output nc inverting input v offset null top view noninverting input 1 4 5 v os trim top view ?5v 10k w one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 to-99 (h) package
AD548Cspecifications model AD548j/a/s AD548k/b AD548c min typ max min typ max min typ max units input offset voltage 1 initial offset 0.75 2.0 0.3 0.5 0.10 0.25 mv t min to t max 3.0/3.0/3.0 0.7/0.8 0.4 mv vs. temperature 20 5 2.0 m v/ c vs. supply 80 86 86 db vs. supply, t min to t max 76/76/76 80 80 db long-term offset stability 15 15 15 m v/month input bias current either input 2 , v cm = 0 5 20 3 10 3 10 pa either input 2 at t max , v cm = 0 0.45/1.3/20 0.25/0.65 0.65 na max input bias current over common-mode voltage range 30 15 15 pa offset current, v cm = 0 510 25 25pa offset current at t max 0.25/0.65/10 0.15/0.35 0.35 na input impedance differential 1 10 12 i 31 10 12 i 31 10 12 i 3 w i pf common mode 3 10 12 i 33 10 12 i 33 10 12 i 3 w i pf input voltage range differential 3 20 20 20 v common mode 11 12 11 12 11 12 v common-mode rejection v cm = 10 v 76 90 82 92 86 98 db t min to t max 76/76/76 90 82 92 86 98 db v cm = 11 v 70 84 76 86 76 90 db t min to t max 70/70/70 84 76 86 76 90 db input voltage noise voltage 0.1 hz to 10 hz 2 2 2 4.0 m v p-p f = 10 hz 80 80 80 nv/ ? hz f = 100 hz 40 40 40 nv/ ? hz f = 1 khz 30 30 30 nv/ ? hz f = 10 khz 30 30 30 nv/ ? hz input current noise f = 1 khz 1.8 1.8 1.8 fa/ ? hz frequency response unity gain, small signal 0.8 1.0 0.8 1.0 0.8 1.0 mhz full power response 30 30 30 khz slew rate, unity gain 1.0 1.8 1.0 1.8 1.0 1.8 v/ m s settling time to 0.01% 8 8 8 m s open loop gain v o = 10 v, r l 3 10 k w 300 1000 300 1000 300 1000 v/mv t min to t max , r l 3 10 k w 300/300/300 700 300 700 300 700 v/mv v o = 10 v, r l 3 5 k w 150 500 150 500 150 500 v/mv t min to t max , r l 3 5 k w 150/150/150 300 150 300 150 300 v/mv output characteristics voltage @ r l 3 10 k w , 12 13 12 13 12 13 v t min to t max 12/ 12/ 12 12 12 voltage @ r l 3 5 k w , 11 12.3 11 12.3 11 12.3 v t min to t max 11/ 11/ 11 11 11 short circuit current 15 15 15 ma power supply rated performance 15 15 15 v operating range 4.5 18 4.5 18 4.5 18 v quiescent current 170 200 170 200 170 200 m a temperature range operating, rated performance commercial (0 c to +70 c) AD548j AD548k industrial (C40 c to +85 c) AD548a AD548b AD548c military (C55 c to +125 c) AD548s package options soic (r-8) AD548jr AD548kr, AD548br plastic (n-8) AD548jn AD548kn cerdip (q-8) AD548aq AD548cq metal can (h-08a) AD548ah AD548bh tape and reel AD548jr-reel AD548kr-reel, AD548br-reel chips available AD548jchips notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperature, the current doubles every 10 c. 3 defined as voltages between inputs, such that neither exceeds 10 v from ground. specifications subject to change without notice. (@ +25 8 c and v s = 6 15 v dc unless otherwise noted) rev. c C2C
AD548 rev. c C3C warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD548 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings l supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 500 mw input voltage 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v output short circuit duration . . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (q, h) . . . . . . . . C65 c to +150 c (n, r) . . . . . . . . C65 c to +125 c operating temperature range AD548j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 c to +70 c AD548a/b/c . . . . . . . . . . . . . . . . . . . . . . . . C40 c to +85 c AD548s . . . . . . . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 8-pin soic package: q ja = 160 c/w, q jc = 42 c/w; 8-pin plastic package: q ja = 90 c/w; 8-pin cerdip package: q jc = 22 c/w, q ja = 110 c/w; 8-pin metal can package: q jc = 65 c/w, q ja = 150 c/w. 3 for supply voltages less than 18 v, the absolute maximum input voltage is equal to the supply voltage. metalization photograph dimensions shown in inches and (mm). contact factory for latest dimensions supply voltage ? v 20 15 10 5 0 input voltage ? v 0 5 10 15 20 +v in ? in figure 1. input voltage range vs. supply voltage supply voltage ? v 200 180 160 140 120 quiescent current ?? 0 5 10 15 20 figure 4. quiescent current vs. supply voltage supply voltage ? v 10 6 4 2 0 input bias current ?pa 0 4 8 12 16 20 8 figure 5. input bias current vs. supply voltage typical characteristics load resistance ? w 30 25 20 10 0 10 100 1k 10k 5 15 output voltage swing ?volts p-p figure 3. output voltage swing vs. load resistance supply voltage ? v 20 15 10 5 0 output voltage swing ? v 0 5 10 15 20 +v out ? out 25 c r l = 10k figure 2. output voltage swing vs. supply voltage temperature ? c 100na input bias current ?5 ?5 5 35 65 95 125 10na 1na 100pa 10pa 1pa 100fa 10fa figure 6. input bias current vs. temperature
common-mode voltage ?v 10 6 4 2 0 input bias current ?pa ?0 ? ? 2 6 10 8 figure 7. input bias current vs. common-mode voltage frequency ?hz 100 80 60 0 ?0 1k 10k 100k 1m 10m ?0 20 40 phase in degrees 100 80 60 0 ?0 ?0 20 40 phase gain open loop gain ?db figure 10. open loop frequency response frequency ?hz 90 80 70 50 20 1k 10k 100k 1m 40 60 cmrr ?db 30 figure 13. cmrr vs. frequency frequency ?hz 4 1 0.001 100 1k 10k 0.01 0.1 total harmonic distortion ?% 100k follower with gain = 10 unity gain follower figure 16. total harmonic distortion vs. frequency AD548Ctypical characteristics temperature ? c 1500 1000 750 500 0 ?5 ?5 5 35 65 95 125 1250 250 r l = 10k open loop gain ?v/mv figure 9. open loop gain vs. temperature frequency ?hz 120 100 80 20 ?0 100 1k 10k 100k 1m 0 40 60 ?upply +supply power supply rejection ?db figure 12. psrr vs. frequency 10mv settling time ?? 10 0 ? ?0 output voltage swing ?v 0 2 4 6 8 5 1mv 1mv 10mv figure 15. output swing and error voltage vs. output settling time source impedance ? w 1,000 100 10 0 100k 1m 10m 100m 1g 10g 100g 10,000 1 amplifier generated noise resistor johnson noise 1khz bandwidth 10hz bandwidth whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for application input noise voltage ?? p-p figure 18. total noise vs. source impedance warm-up time ?seconds 30 20 15 10 0 0 10 20 30 40 50 60 70 25 5 i d v os i ? m v figure 8. change in offset voltage vs. warm-up time supply voltage ? v 120 100 90 80 60 open loop voltage gain ?db 0 2 4 6 8 10 12 14 16 18 110 70 figure 11. open loop voltage gain vs. supply voltage output voltage ?v p-p frequency ?hz 22 20 18 12 8 10 100 1k 10k 100k 1m 10 14 16 0 6 4 2 figure 14. large signal frequency response frequency ?hz 160 140 120 60 20 10 100 1k 10k 100k 40 80 100 0 input noise voltage ?nv/ ? hz figure 17. input noise voltage spectral density C4C rev. c
typical characteristicsCAD548 figure 19c. unity gain follower pulse response (small signal) figure 19b. unity gain follower pulse response (large signal) figure 20c. unity gain inverter pulse response (small signal) figure 20b. utility gain inverter pulse response (large signal) application notes the AD548 is a jfet-input op amp with a guaranteed maxi- mum i b of less than 10 pa, and offset and drift laser-trimmed to 0.25 mv and 2 m v/ c respectively (AD548c). ac specs in- clude 1 mhz bandwidth, 1.8 v/ m s typical slew rate and 8 m s set- tling time for a 20 v step to 0.01%all at a supply current less than 200 m a. to capitalize on the devices performance, a num- ber of error sources should be considered. the minimal power drain and low offset drift of the AD548 reduce self-heating or warm-up effects on input offset voltage, making the AD548 ideal for on/off battery powered applica- tions. the power dissipation due to the AD548s 200 m a supply current has a negligible effect on input current, but heavy out- put loading will raise the chip temperature. since a jfets in- put current doubles for every 10 c rise in chip temperature, this can be a noticeable effect. the amplifier is designed to be functional with power supply voltages as low as 4.5 v. it will exhibit a higher input offset voltage than at the rated supply voltage of 15 v, due to power supply rejection effects. the common-mode range of the AD548 extends from 3 v more positive than the negative supply to 1 v more negative than the positive supply. designed to cleanly drive up to 10 k w and 100 pf loads, the AD548 will drive a 2 k w load with reduced open loop gain. offset nulling unlike bipolar input amplifiers, zeroing the input offset voltage of a bifet op amp will not minimize offset drift. using balance pins 1 and 5 to adjust the input offset voltage as shown in fig- ure 21 will induce an added drift of 0.24 m v/ c per 100 m v of nulled offset. the low initial offset (0.25 mv) of the AD548c results in only 0.6 m v/ c of additional drift. rev. c C5C figure 19a. unity gain follower figure 20a. utility gain inverter applying the AD548 figure 21. offset null configuration layout to take full advantage of the AD548s 10 pa max input current, parasitic leakages must be kept below an acceptable level. the practical limit of the resistance of epoxy or phenolic circuit board material is between 1 10 12 w and 3 10 12 w . this can result in an additional leakage of 5 pa between an input of 0 v and a C15 v supply line. teflon or a similar low leakage material (with a resistance exceeding 10 17 w ) should be used to isolate high impedance input lines from adjacent lines carrying high voltages. the insulator should be kept clean, since contaminants will degrade the surface resistance. a metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input po- tential can also be used to reduce some parasitic leakages. the guarding pattern in figure 22 will reduce parasitic leakage due to finite board surface resistance; but it will not compensate for a low volume resistivity board.
AD548 C6C rev. c figure 22. board layout for guarding inputs input protection the AD548 is guaranteed to withstand input voltages equal to the power supply potential. exceeding the negative supply volt- age on either input will forward bias the substrate junction of the chip. the induced current may destroy the amplifier due to excess heat. input protection is required in applications such as a flame detector in a gas chromatograph, where a very high potential may be applied to the input terminals during a sensor fault con- dition. figure 23 shows a simple current limiting scheme that can be used. r protect should be chosen such that the maxi- mum overload current is 1.0 ma (l00 k w for a 100 v overload, for example). exceeding the negative common-mode range on either input terminal causes a phase reversal at the output, forcing the amplifier output to the corresponding high or low state. exceed- ing the negative common-mode on both inputs simultaneously forces the output high. exceeding the positive common-mode range on a single input doesnt cause a phase reversal, but if both inputs exceed the limit the output will be forced high. in all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range. figure 23. input protection of iv converter d/a converter output buffer the circuit in figure 24 shows the AD548 and ad7545 12-bit cmos d/a converter in a unipolar binary configuration. v out will be equal to v ref attenuated by a factor depending on the digital word. v ref sets the full scale. overall gain is trimmed by adjusting r in . the AD548s low input offset voltage, low drift and clean dynamics make it an attractive low power output buffer. the input offset voltage of the AD548 output amplifier results in an output error voltage. this error voltage equals the input offset voltage of the op amp times the noise gain of the amplifier. figure 24. AD548 used as dac output amplifier that is: v os output = v os input 1 + r fb r o ? ? ? ? r fb is the feedback resistor for the op amp, which is internal to the dac. r o is the dacs r-2r ladder output resistance. the value of r o is code dependent. this has the effect of changing the offset error voltage at the amplifiers output. an output am- plifier with a sub millivolt input offset voltage is needed to preserve the linearity of the dacs transfer function. the AD548 in this configuration provides a 700 khz small sig- nal bandwidth and 1.8 v/ m s typical slew rate. the 33 pf capaci- tor across the feedback resistor optimizes the circuits response. the oscilloscope photos in figures 25 and 26 show small and large signal outputs of the circuit in figure 24. upper traces show the input signal v in . lower traces are the resulting output voltage with the dacs digital input set to all 1s. the AD548 settles to 0.01% for a 20 v input step in 14 m s. 0% 10 5v 5? 20v 100 90 figure 25. response to 20 v p-p reference square wave 0% 10 50mv 2? 200mv 100 90 figure 26. response to 100 mv p-p reference square wave
figure 29. low power instrumentation amplifier gains of 1 to 100 can be accommodated with gain nonlinearities of less than 0.01%. referred to input errors, which contribute an output error proportional to in amp gain, include a maxi- mum untrimmed input offset voltage of 0.5 mv and an input offset voltage drift over temperature of 4 m v/ c. output errors, which are independent of gain, will contribute an additional 0.5 mv offset and 4 m v/ c drift. the maximum input current is 15 pa over the common-mode range, with a common-mode impedance of over 1 10 12 w . resistor pairs r3/r5 and r4/r6 should be ratio matched to 0.01% to take full advantage of the AD548s high common-mode rejection. capacitors c1 and c1 compensate for peaking in the gain over frequency caused by input capacitance when gains of 1 to 3 are used. the C3 db small signal bandwidth for this low power instru- mentation amplifier is 700 khz for a gain of 1 and 10 khz for a gain of 100. the typical output slew rate is 1.8 v/ m s. log ratio amplifier log ratio amplifiers are useful for a variety of signal condition- ing applications, such as linearizing exponential transducer out- puts and compressing analog signals having a wide dynamic range. the AD548s picoamp level input current and low input offset voltage make it a good choice for the front-end amplifier of the log ratio circuit shown in figure 30. this circuit produces an output voltage equal to the log base 10 of the ratio of the in- put currents i 1 and i 2 . resistive inputs r1 and r2 are provided for voltage inputs. input currents i 1 and i 2 set the collector currents of q1 and q2, a matched pair of logging transistors. voltages at points a and b are developed according to the following familiar diode equation: v be = ( kt / q )ln( i c / i es ) in this equation, k is boltzmanns constant, t is absolute tem- perature, q is an electron charge, and i es is the reverse saturation current of the logging transistors. the difference of these two voltages is taken by the subtractor section and scaled by a factor of approximately 16 by resistors r9, r10, and r8. temperature application hintsCAD548 photodiode preamp the performance of the photodiode preamp shown in figure 27 is enhanced by the AD548s low input current, input voltage offset and offset voltage drift. the photodiode sources a current proportional to the incident light power on its surface. r f converts the photodiode current to an output voltage equal to r f i s . figure 27. an error budget illustrating the importance of low amplifier input current, voltage offset and offset voltage drift to minimize output voltage errors can be developed by considering the equi- valent circuit for the small (0.2 mm 2 area) photodiode shown in figure 27. the input current results in an error proportional to the feedback resistance used. the amplifiers offset will produce an error proportional to the preamps noise gain (i + r f /r sh ), where r sh is the photodiode shunt resistance. the amplifiers input current will double with every 10 c rise in temperature, and the photodiodes shunt resistance halves with every 10 c rise. the error budget in figure 28 assumes a room temperature photodiode r sh of 500 m w , and the maximum input current and input offset voltage specs of an AD548c. temp 8 cr sh (m v )v os ( m v) (1+ r f /r sh ) v os i b (pa) i b r f total C 25 15,970 150 151 m v 0.30 30 m v 181 m v 0 2,830 200 207 m v 2.26 262 m v 469 m v +25 500 250 300 m v 10.00 1.0 mv 1.30 mv +50 88.5 300 640 m v 56.6 5.6 mv 6.24 mv +75 15.6 350 2.6 mv 320 32 mv 34.6 mv +85 7.8 370 5.1 mv 640 64 mv 69.1 mv figure 28. photo diode pre-amp errors over temperature the capacitance at the amplifiers negative input (the sum of the photodiodes shunt capacitance, the op amps differential input capacitance, stray capacitance due to wiring, etc.) will cause a rise in the preamps noise gain over frequency. this can result in excess noise over the bandwidth of interest. c f reduces the noise gain peaking at the expense of bandwidth. instrumentation amplifier the AD548cs maximum input current of 10 pa makes it an excellent building block for the high input impedance instru- mentation amplifier shown in figure 29. total current drain for this circuit is under 600 m a. this configuration is optimal for conditioning differential voltages from high impedance sources. the overall gain of the circuit is controlled by r g , resulting in the following transfer function: v out v in = 1 + ( r 1 + r 2 ) r g rev. c C7C
AD548 C8C rev. c printed in u.s.a. c999aC19C12/86 outline dimensions dimensions shown in inches and (mm). figure 30. log ratio amplifier compensation is provided by resistors r8 and r15, which have a positive 3500 ppm/ c temperature coefficient. the transfer function for the output voltage is: v out = 1 v log 10 ( i 2 / i 1 ) frequency compensation is provided by r11, r12, c1, and c2. small signal bandwidth is approximately 300 khz at input cur- rents above 100 m a and will proportionally decrease with lower signal levels. d1, d2, r13, and r14 compensate for the effects of the two logging transistors ohmic emitter resistance. to trim this circuit, set the two input currents to 10 m a and ad- just v out to zero by adjusting the potentiometer on a3. then set i 2 to 1 m a and adjust the scale factor such that the output voltage is 1 v by trimming potentiometer r10. offset adjust- ment for a1 and a2 is provided to increase the accuracy of the voltage inputs. this circuit ensures a 1% log conformance error over an input current range of 300 pa to 1 ma, with low level accuracy limited by the AD548s input current. the low level input volt- age accuracy of this circuit is limited by the input offset voltage and drift of the AD548. to-99 (h) package soic (r) package plastic mini-dip (n) package cerdip (q) package
|
